(1) Field of the Invention
The present invention relates to a processing device in which processors are included on a single chip, and in particular, to a processing device in which a cache memory shared by the processors is included.
(2) Description of the Related Art
Technical development in processing devices in which processors are included on a single chip has intensified in recent years. Furthermore, in such a processing device, it is typical that a cache memory is included in processors in order to improve processing performance. Thus, sharing a cache memory among processors becomes important. Accordingly, various techniques for sharing a cache memory among processors have been conventionally proposed (for instance, refer to Japanese Unexamined Patent Application Publication No. 01-280860).
However, in order to have processors share the above-described cache memory, each processor has a data port, and the number of data lines corresponding to the data ports is provided. A data port is a collective designation for an output port through which data is read from a cache memory and an input port through which data is written into a cache memory.
For instance, consider, as an example, a case where a cache memory capable of reading and writing 128-bit data is shared by two processors. In this case, for data lines, at least two sets of signal lines corresponding to the 128 bits are required. Therefore, even with cache memories having the same capacity, there is a problem in that the circuit area of a cache memory having a multi-port data port increases in comparison to that of a cache memory having a single-port dataport. In addition, the number of dataports increases as the number of processors increases. As a result, the above-described problem becomes more prominent as the number of processors increases.